A new custom VLSI circuit for dynamic time warping is described; it can be used for both isolated and connected speech recognition, with both templates and discrete hidden Markov models (D.H.M.M.). The chip has an Harvard architecture, with an internal program ROM horizontally microcoded and an external data memory up to 16 Mbytes: an internal cache relaxes speed requirements for the external data RAM. A separate address generation block and an arithmetic unit specialized to the dynamic programming task complete the internal chip structure. With a clock of 16 MHz. the microinstruction cycle is of 125 nsec.; we have evaluated a task speed up of about 5 in comparison to a DSP implementation. The chip is implemented in a 3 micron 2 metal levels CMOS technology, with a complexity of 70K equivalent transistors and a die size of 6 mm. by 5.5 mm.; it is housed in 68 pins LCC package.
Bibliographic reference. Cecinati, Riccardo / Ciaramella, Alberto / Licciardi, Luigi / Venuti, Giovanni (1989): "Implementation of a dynamic time warp integrated circuit for large vocabulary isolated and connected speech recognition", In EUROSPEECH-1989, 1565-1568.