A multiprocessor architecture for high complexity speech processing is described that uses groups of 4 DSP chips each in a hierarchical, reconfigurable structure, yielding some 100 MFlops per board. This architecture combines low amount of hardware with high efficiency for many speech applications. The software environment is based on available development tools and can easily be adapted to future DSP components.
Bibliographic reference. Schultheiß, M. / Lacroix, A. (1991): "Fast hardware for efficient parallel processing of speech signals", In EUROSPEECH-1991, 1353-1356.