Fourth European Conference on Speech Communication and Technology

Madrid, Spain
September 18-21, 1995

Hardware Design of LPC Coding for Speech Feature Extraction

M. Li, J. T. Proudfoot

Department of Electrical & Electronic Engineering, University College of Swansea, Swansea, UK, and
N. Ireland Bio-Engineering Centre, University of Ulster at Jordanstown, Co Antrim, N. Ireland, UK

This paper describes the high-level design and specification of an Application-Specific Integrated Circuit (ASIC) to implement a speech feature extraction algorithm based on Linear Predictive Coding (LPC). The ASIC uses a fully synchronous top-down design methodology with a hardware description language ELLA. To suit the hardware design, the LPC algorithm is reformulated. A register-transfer level structure is used to meet requirements for suitability and efficiency of hardware, and a hierarchical design methodology used to implement the algorithm in low cost ASIC form. The approach can be applied to a wide range of digital signal processing functions. The goal of this effort is to develop a speaker recognition system based on the LPC algorithm which can be used as an alternative to the currently used software system.

Full Paper

Bibliographic reference.  Li, M. / Proudfoot, J. T. (1995): "Hardware design of LPC coding for speech feature extraction", In EUROSPEECH-1995, 157-160.