First International Conference on Spoken Language Processing (ICSLP 90)

Kobe, Japan
November 18-22, 1990

An Accelerator for High-Speed Spoken Word-Spotting and Noise Immunity Learning System

Hiroyuki Tsuboi, Hiroshi Kanazawa, Yoichi Takebayashi

Toshiba Corporation, Research & Development Center, Kawasaki, Japan

An accelerator utilizing four digital signal processors (DSPs) has been developed to facilitate real-time speech recognition. The accelerator has been implemented in a real-time robust speaker-independent word recognition system. This system employs word-spotting based on Noise Immunity Learning to avoid word boundary detection errors and to increase recognition accuracy in noisy environments. The accelerator board, including four DSPs with shared memory, has 132 MFLOPS peak performance. Since more than 90% of the computational load is inner product calculation, the DSPs share a vocabulary for the purpose of load-balancing. The architecture of the accelerator consists of off-the-shelf components connected in such a way for improved performance in the application. The speed of a single accelerator was shown to be approximately 20 times faster than that of a current high speed workstation with 32 MFLOPS peak performance.

Full Paper

Bibliographic reference.  Tsuboi, Hiroyuki / Kanazawa, Hiroshi / Takebayashi, Yoichi (1990): "An accelerator for high-speed spoken word-spotting and noise immunity learning system", In ICSLP-1990, 273-276.