First International Conference on Spoken Language Processing (ICSLP 90)
In this paper, we propose a dedicated architecture for the Viterbi scoring in hidden Markov model(HMM)-based real-time isolated word recognition systems. Since, in HMM, most states are connected to only three or fewer preceding states, the state transition matrix is very sparse and upper diagonal. Using this property of HMM, we design an efficient Viterbi scoring architecture. The proposed architecture is constructed using either of two types of processing elements (PEs); one can process efficiently most HMM topologies that are being used in practice with a very simple hardware structure, and the other is designed to cover almost all of the possible HMM topologies at an additional hardware cost. Each PE processes, one trellis stage. The PEs can be cascaded to process several consecutive trellis stages in pipeline, thus the memory I/O bandwidth requirement is relaxed significantly. The proposed PEs are implemented in the digit-serial fashion. Thus, the hardware cost of the circuit and the pin count for off-chip I/O is kept to a minimum. Also, since the operators are pipelined fully at digit-level, higher throughput can be obtained.
Bibliographic reference. Kim, Jin Yul / Cho, Yun Seok / Yoon, Soon Young / Lee, Hwang Soo / Un, Chong Kwan (1990): "An efficient viterbi scoring architecture for HMM-based isolated word recognition systems", In ICSLP-1990, 541-544.